返回列表 发帖

请教各位高手sci与smi#的区别是什么呀?

对于smi#还比较了解,自己加过。可sci不是太清楚。请各位大虾指教一下。

sci:system control interrupt    smi:system         management interrupt   
我也不清楚,嘿嘿

[ 本帖最后由 rightnow51 于 2008-8-15 16:35 编辑 ]

TOP

sci:system control interrupt . 通俗地讲只能用ACPI method 来处理这个interrupt.
至于smi 大家都很熟悉了。

TOP

同意
修得一身好灵气,万事花开万事春。-- 争取每日一帖!

TOP

SMI:system management interrupt,系统管理中断,进入SMM的方法,包含(但不限于)电源管理功能,对OS透明的;
SCI:system control interrupt,系统控制中断,是ACPI定义的,专用于ACPI电源管理的一个IRQ,需要OS支持的。

联系:都可以用于电源管理功能
区别:SMI是CPU级别的,ACPI和非ACPI模式下都可以用;SCI是OS级别的,只有在ACPI模式才可以用。

个人理解。
studying

TOP

在ACPI_EN模式下,SCI事件会引起ICH里面的ACPI General purpose event register 状态位的改变, ASL code里面的GPE_Lxx方法会向OS通知发生了那种事件.
What I said here are only my personel statements and do not represent Intel.

TOP

谢谢各位高手的帮助了。

TOP

System Control Interrupt (SCI)
SCI is a system interrupt used by hardware to notify the operating system of ACPI events.
The SCI is an active, low, shareable, level interrupt.  

System Management Interrupt (SMI)
SMI is an OS-transparent interrupt generated by interrupt events on legacy systems. By
contrast, on ACPI systems, interrupt events generate an OS-visible interrupt that is shareable
(edge-style interrupts will not work).

TOP

好不容易发现一个可以回答的问题,都被你们说了。
我本将心向明月。。。。。。。

TOP

回复 9# 的帖子

加油加油~~
Let's study together!

TOP

SMI handler肯定在SMRAM里面
SCI handler嘛,肯定不在SMRAM里面,而且肯定是用ASL写的

TOP

SMI#/SCI Generation

On any SMI# event taking place, ICH9 asserts SMI# to the processor, which causes it
to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is
set, SMI# goes inactive for a minimum of 4 PCI clocks. If another SMI event occurs,
SMI# is driven active again.

The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.

In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not . The interrupt remains asserted until all SCI sources are removed.

Note that some events can be programmed to cause either an SMI# or SCI. The usage of the event for SCI (instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI source has a corresponding enable and status bit.

上面这段话是从ICH9 SPEC 里面拷贝出来的,我想应该讲的很清楚。不过对SCI 产生到系统处理还是不够了解,希望大家继续讨论!
比方说Power Button 连接在一个GPIO上,我们将它配置成上升或者下降或者电平触发SCI, 当这个SCI 产生以后,它是系统共过轮巡的方式发现这个事件,然后调用我们用ASL code 写得shut down 的method 呢还是SCI 重向到IRQ9, 然后通知系统有事件发生?
把每一天当作人生的最后一天,让生活精彩纷呈

TOP

调用ASL CODE,所谓的SCI handler

TOP

SMI 可用于 legacy system 和 ACPI system  对OS透明。
SCI 可用于 ACPI system  需要OS支持。

看看ICH10上是怎么介绍的:
SMI#/SCI Generation
On any SMI# event taking place, ICH10 asserts SMI# to the processor, which causes it
to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is
set, SMI# goes inactive for a minimum of 4 PCI clocks. If another SMI event occurs,
SMI# is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see Section 13.1.3). The interrupt remains asserted until all SCI
sources are removed.
Table 5-28 shows which events can cause an SMI# and SCI. Note that some events can
be programmed to cause either an SMI# or SCI. The usage of the event for SCI
(instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI
source has a corresponding enable and status bit.


NOTES:
1. SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
2. SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
3. GBL_SMI_EN must be 1 to enable SMI.
4. EOS must be written to 1 to re-enable SMI for the next 1.
5. ICH10 must have SMI# fully enabled when ICH10 is also enabled to trap cycles. If SMI# is
not enabled in conjunction with the trap enabling, then hardware behavior is undefined.
6. Only GPI[15:0] may generate an SMI# or SCI.
7. When a power button override first occurs, the system will transition immediately to S5.
The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)
is not cleared prior to setting SCI_EN.
8. This SMI is a synchronous event.

TOP

知识是要大家分享才能更快的提高的,有我知道的也一定会回答各位的。。谢了

TOP

学习了  谢谢。。。
\o(∩“欲不欲”,“学不学”,循道而作∩)o/

TOP

写的真不错,受教了。谢谢大家

TOP

12# BlueStone
应该是 SCI 导致 IRQ to CPU,CPU 跳到 事先安装好的中断句柄处(ACPI driver),ACPI Driver 再去调用ASL ,然后告知OS 吧~!~!

TOP

我觉得其实这两个区别不是很大,你就当它们都是中断就行了,只不过是两个特殊的中断,你可以设定SCI event 产生普通interupt,SMI,SCI。例如你可以disable SCI,而enable SMI。
1。不过发SMI的话,handler 应该是在bios中,由于bios 大小的限制,smi handler 完成的工作可能不多,而SCI hander 一版是APCI driver and asl code 做的,可以做很多事。
2。smi 是边沿触发,可能会导致某些SMI 丢失。
3。SMI handler 工作在SM mode 下,CPU 的all logical CPU 都将进入SM mode下,而SCI 则可以只发给某个logical cpu,增加了系统性能。
所以现在OS下,会优先考虑使用SCI。
我也是新手,以上只是我个人浅见,如果有什么问题,请不吝指教。

TOP

2。smi 是边沿触发,可能会导致某些SMI 丢失。
第一次知道这个,学习了

TOP

返回列表